The 3rd edition of the ASYNC Summer school will be co-located directly before the conference 1-2 June 2026 as a hybrid event at DTU in Lyngby, Denmark.<\/p>\n
The goal of the school is to teach asynchronous chip design to students and practitioners interested in digital hardware design. Participants will learn how to design asynchronous circuits at the behavioral level, gate level, and physical design level using design automation tools<\/p>\n
Call for participation to the community:<\/strong> we are searching for additional lectures, please contact the summer school chairs to discuss further!<\/p>\n The Program is still in development, please check for updates!<\/p>\n https:\/\/avlsi.csl.yale.edu\/act\/doku.php?id=summer2026:start<\/a><\/p>\n Session 1. June 1 – Morning: Behavioral design<\/strong> – Overview of summer school + introduction to async Session 2. June 1 – Afternoon: From behavior to gates<\/strong> – Handshake Protocols Session 3. June 2 Morning: Physical design<\/strong> – Timing and Static timing analysis Session 4. June 2 – Afternoon: Special Topics & Social evening event<\/strong><\/p>\n detailed program and registration will follow!<\/p>\n https:\/\/avlsi.csl.yale.edu\/act\/doku.php?id=summer2026:start<\/a><\/p>\n","protected":false},"excerpt":{"rendered":" The 3rd edition of the ASYNC Summer school will be co-located directly before the conference 1-2 June 2026 as a hybrid event at DTU in Lyngby, Denmark. The goal of the school is to teach asynchronous chip design to students and practitioners interested in digital hardware design. Participants will learn how to design asynchronous circuits … Continue reading Summer School<\/span>
\nThis session covers the abstractions used for the behavioral description of asynchronous circuits, and how one can use simulation at this level of abstraction to test the functionality of an asynchronous design.<\/p>\n
\n– Behavioral design with message-passing
\n– Dataflow Design
\n– Design with High Level Syntheses<\/p>\n
\nThis session covers systematic techniques to translate the detailed
\nsignal-level description of an asynchronous computation into gates.<\/p>\n
\n– Synthesis and Cells
\n– Syntax Directed Translation<\/p>\n
\nThis session covers mapping a gate-level description of a design into a physical implementation.<\/p>\n
\n– Cell mapping
\n– Place and Route<\/p>\n