{"id":193,"date":"2026-04-17T07:07:41","date_gmt":"2026-04-17T07:07:41","guid":{"rendered":"https:\/\/asyncsymposium.org\/async2026\/?page_id=193"},"modified":"2026-04-17T10:44:39","modified_gmt":"2026-04-17T10:44:39","slug":"program","status":"publish","type":"page","link":"https:\/\/asyncsymposium.org\/async2026\/program\/","title":{"rendered":"Program"},"content":{"rendered":"

Keynotes<\/h2>\n

\"\"Industrializing an asynchronous technology: Tiempo from 2007 to 2025 <\/b>
\nby Marc Renaudin (Qualcomm Technologies Inc.)<\/p>\n

 <\/p>\n

 <\/p>\n

\"\"<\/p>\n

Keynote 2<\/b> by Federico Corradi (Technical University of Eindhoven)<\/p>\n

<\/h2>\n

Program<\/h2>\n

1-2 June Summer School<\/a><\/h3>\n

3. June<\/h3>\n

<\/p>\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n
Wednesday 3rd<\/caption>\n
Time<\/th>\nEvent<\/th>\n<\/tr>\n<\/thead>\n
08:00<\/td>\nRegistration & breakfast snacks<\/td>\n<\/tr>\n
09:00<\/td>\nWelcome<\/td>\n<\/tr>\n
09:15<\/td>\nSession: Asynchronous circuit Synthesis (1h30)<\/p>\n
    \n
  1. Taking Timing Out of the Equation: Moving Fully Automated Synthesis as close as possible to Delay-Insensitive Circuits<\/strong>
    \nAuthors:<\/em> Karthi Srinivasan, Ole Richter, Jordan Schmerge and Rajit Manohar<\/li>\n
  2. Generalized Binary Comparator Networks for QDI Combinational Logic Synthesis<\/strong>
    \nAuthors:<\/em> Florian Huemer and Dylan Baumann<\/li>\n
  3. Improved Logic Synthesis for Asynchronous Circuits<\/strong>
    \nAuthors:<\/em> Karthi Srinivasan and Rajit Manohar<\/li>\n<\/ol>\n<\/td>\n<\/tr>\n
10:45<\/td>\nBreak (coffee & snacks)<\/td>\n<\/tr>\n
11:10<\/td>\nKeynote Industrializing an asynchronous technology: Tiempo from 2007 to 2025 <\/b>by Marc Renaudin<\/td>\n<\/tr>\n
12:10<\/td>\n\u00a0Lunch in the Faculty Club<\/td>\n<\/tr>\n
13:10<\/td>\nSession: Test of the asynchronous circuits (1h50)<\/p>\n
    \n
  1. A-ATPG: A Graph-based Automatic Test Pattern Generation Method for the DfT Architecture of Asynchronous Bundled-data Circuits<\/strong>
    \nAuthors:<\/em> Xuanyu Zhang, Jilin Zhang, Marly Roncken and Hong Chen<\/li>\n
  2. A Test Architecture for Bundled-Data Asynchronous NoC Switches Using Commercial ATPG Tools<\/strong>
    \nAuthors:<\/em> Iordana Gaisidou, Giuseppe Chessa, Giannoulas Ioannis, Artur Jutman, Davide Bertozzi and Christos Sotiriou<\/li>\n
  3. Jumper: A State Capturing Element For Testability in Asynchronous Bundled-Data Circuits<\/strong>
    \nAuthors:<\/em> Ismael de Almeida Junior, Azzadine THAJTE, Cristiano Merio, Xavier Lesage, Adrien Godard, Ali Naimi, Sylvain Engels and Laurent Fesquet<\/li>\n
  4. Automated FPGA-Based Wafer Testing of Asynchronous FlexICs<\/strong>
    \nAuthors:<\/em> Marcos Luiggi Lemos Sartori, Yushu Qin, Shengyu Duan, Yujin Zheng, Rishad Shafik and Alex Yakovlev<\/li>\n<\/ol>\n<\/td>\n<\/tr>\n
15:00<\/td>\nBreak (coffee & snacks)<\/td>\n<\/tr>\n
15:30<\/td>\nDemo Session (1h)<\/p>\n
    \n
  1. ACTGen: Natural Language Assistant for Asynchronous Circuit Design<\/strong>
    \nAuthors:<\/em> Siva Nalabothu and Rajit Manohar<\/li>\n
  2. ALPS: An Open-Source Low-Power Bundled-Data Design Flow using Standard EDA Tools<\/strong>
    \nAuthors:<\/em> Cristiano Merio, Adrien Godard, Ga\u00ebl Ousset, Xavier Lesage, J\u00e9ssica Gonsalves Santos, Ismael de Almeida Junior, Ali Naimi, Azzadine Thajte, Ayoub Talbi, Thierry Grollier, Marc Quast, Sylvain Engels and Laurent Fesquet<\/li>\n<\/ol>\n<\/td>\n<\/tr>\n
16:30<\/td>\nHead to Copenhagen Center & short optional city walk<\/td>\n<\/tr>\n
19:00<\/td>\nConference Dinner<\/td>\n<\/tr>\n<\/tbody>\n<\/table>\n

<\/p>\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n
Thursday 4th<\/caption>\n
Time<\/th>\nEvent<\/th>\n<\/tr>\n<\/thead>\n
08:00<\/td>\nBreakfast snacks & coffee<\/td>\n<\/tr>\n
09:00<\/td>\nFresh idea session (1h20)<\/p>\n
    \n
  1. Easy Timers for AFSM-based Controllers in Workcraft<\/strong>
    \nAuthors:<\/em> Victor Khomenko and Danil Sokolov<\/li>\n
  2. Applications of asynchronous logic in power management and protection ICs<\/strong>
    \nAuthors:<\/em> David Cox and Filip Hormot<\/li>\n
  3. Templated and open asynchronous periphery for mixed-signal neuromorphic chips\u00a0<\/strong>
    \nAuthors: Hugh Gratorex, Madison Cotterert, Michele Mastella, Arianna Rubino, Ole Richter and Elisabetta Chicca<\/li>\n
  4. Explicit Timestamp Propagation for Temporal Processing<\/strong>
    \nAuthors:<\/em> Xavier Lesage, Cristiano Merio, Azzadine THAJTE, Luca Sauer de Araujo, Fernando Welzel, Sylvain Engels and Laurent Fesquet<\/li>\n<\/ol>\n<\/td>\n<\/tr>\n
10:20<\/td>\nBreak (coffee & snacks)<\/td>\n<\/tr>\n
10:40<\/td>\nSession: Asynchronous circuit applications and models (1h30)<\/p>\n
    \n
  1. An Energy-Proportional, High-Speed Serial Link<\/strong>
    \nAuthors:<\/em> Alex Huang, Robert Soule and Rajit Manohar<\/li>\n
  2. ANP-E: A 22-nm Asynchronous Spiking Recurrent Neural Network Processor Enabling On-chip Learning for Physiological Signal Monitoring<\/strong>
    \nAuthors:<\/em> Yuan Hua, Chunqi Qian, Jilin Zhang and Hong Chen<\/li>\n
  3. Amplifier Circuit-based Metastability Model<\/strong>
    \nAuthors:<\/em> J\u00fcrgen Burin, Afsah Anjum and Andreas Steininger<\/li>\n<\/ol>\n<\/td>\n<\/tr>\n
12:10<\/td>\nLunch in the Faculty Club<\/td>\n<\/tr>\n
13:10<\/td>\nKeynote 2 by Federico Corradi<\/td>\n<\/tr>\n
14:10<\/td>\nShort break<\/td>\n<\/tr>\n
14:25<\/td>\nPanel: “Open challenges for asynchronous digital integrated circuits in neuronal network hardware”<\/p>\n

Moderator:<\/em> Ole Richter<\/td>\n<\/tr>\n

15:10<\/td>\nBreak<\/td>\n<\/tr>\n
15:30<\/td>\nSession: Efficient bundled-data and NEMS circuits<\/p>\n
    \n
  1. Asymmetric Current-Starved Inverter Delay Lines for High-Performance Bundled-Data Circuits<\/strong>
    \nAuthors:<\/em> J\u00e9ssica Gonsalves Santos, Cristiano Merio, Adrien Godard, Ali Naimi, Robin Wilson, Sylvain Engels and Laurent Fesquet<\/li>\n
  2. Effect of Self-Timed Design Styles on the Lifetime of NEMS Circuits<\/strong>
    \nAuthors:<\/em> Philipp Lehninger, Andreas Steininger and Axel Jantsch<\/li>\n
  3. 74% Power Reduction in Bundled-Data Circuits Thanks to Clock Gating Integration<\/strong>
    \nAuthors:<\/em> Adrien Godard, Laurent Fesquet, Sylvain Engels and Robin Wilson<\/li>\n<\/ol>\n<\/td>\n<\/tr>\n
16:30<\/td>\nClosing session and Best Paper Award<\/td>\n<\/tr>\n
16:50<\/td>\nMove to Copenhagen Center – visit Streetfood market Reffen (alternative program for bad weather)<\/td>\n<\/tr>\n<\/tbody>\n<\/table>\n

<\/p>\n\n\n\n
Friday 5th<\/caption>\n
TBA<\/td>\nSocial event & cultural excursion<\/td>\n<\/tr>\n<\/tbody>\n<\/table>\n","protected":false},"excerpt":{"rendered":"

Keynotes Industrializing an asynchronous technology: Tiempo from 2007 to 2025 by Marc Renaudin (Qualcomm Technologies Inc.)     Keynote 2 by Federico Corradi (Technical University of Eindhoven) Program 1-2 June Summer School 3. June Wednesday 3rd Time Event 08:00 Registration & breakfast snacks 09:00 Welcome 09:15 Session: Asynchronous circuit Synthesis (1h30) Taking Timing Out of … Continue reading Program<\/span> →<\/span><\/a><\/p>\n","protected":false},"author":17,"featured_media":0,"parent":0,"menu_order":0,"comment_status":"closed","ping_status":"closed","template":"","meta":{"footnotes":""},"_links":{"self":[{"href":"https:\/\/asyncsymposium.org\/async2026\/wp-json\/wp\/v2\/pages\/193"}],"collection":[{"href":"https:\/\/asyncsymposium.org\/async2026\/wp-json\/wp\/v2\/pages"}],"about":[{"href":"https:\/\/asyncsymposium.org\/async2026\/wp-json\/wp\/v2\/types\/page"}],"author":[{"embeddable":true,"href":"https:\/\/asyncsymposium.org\/async2026\/wp-json\/wp\/v2\/users\/17"}],"replies":[{"embeddable":true,"href":"https:\/\/asyncsymposium.org\/async2026\/wp-json\/wp\/v2\/comments?post=193"}],"version-history":[{"count":23,"href":"https:\/\/asyncsymposium.org\/async2026\/wp-json\/wp\/v2\/pages\/193\/revisions"}],"predecessor-version":[{"id":219,"href":"https:\/\/asyncsymposium.org\/async2026\/wp-json\/wp\/v2\/pages\/193\/revisions\/219"}],"wp:attachment":[{"href":"https:\/\/asyncsymposium.org\/async2026\/wp-json\/wp\/v2\/media?parent=193"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}