The 3rd edition of the ASYNC Summer school will be co-located directly before the conference 1-2 June 2026 as a hybrid event at DTU in Lyngby, Denmark.
The goal of the school is to teach asynchronous chip design to students and practitioners interested in digital hardware design. Participants will learn how to design asynchronous circuits at the behavioral level, gate level, and physical design level using design automation tools
Call for participation to the community: we are searching for additional lectures, please contact the summer school chairs to discuss further!
The Program is still in development, please check for updates!
https://avlsi.csl.yale.edu/act/doku.php?id=summer2026:start
Session 1. June 1 – Morning: Behavioral design
This session covers the abstractions used for the behavioral description of asynchronous circuits, and how one can use simulation at this level of abstraction to test the functionality of an asynchronous design.
– Overview of summer school + introduction to async
– Behavioral design with message-passing
– Dataflow Design
– Design with High Level Syntheses
Session 2. June 1 – Afternoon: From behavior to gates
This session covers systematic techniques to translate the detailed
signal-level description of an asynchronous computation into gates.
– Handshake Protocols
– Synthesis and Cells
– Syntax Directed Translation
Session 3. June 2 Morning: Physical design
This session covers mapping a gate-level description of a design into a physical implementation.
– Timing and Static timing analysis
– Cell mapping
– Place and Route
Session 4. June 2 – Afternoon: Special Topics & Social evening event
detailed program and registration will follow!