1. Taking Timing Out of the Equation: Moving Fully Automated Synthesis as close as possible to Delay-Insensitive Circuits
   Authors: Karthi Srinivasan, Ole Richter, Jordan Schmerge and Rajit Manohar
2. Generalized Binary Comparator Networks for QDI Combinational Logic Synthesis
   Authors: Florian Huemer and Dylan Baumann
3. Improved Logic Synthesis for Asynchronous Circuits
   Authors: Karthi Srinivasan and Rajit Manohar

1. A-ATPG: A Graph-based Automatic Test Pattern Generation Method for the DfT Architecture of Asynchronous Bundled-data Circuits
   Authors: Xuanyu Zhang, Jilin Zhang, Marly Roncken and Hong Chen
2. A Test Architecture for Bundled-Data Asynchronous NoC Switches Using Commercial ATPG Tools
   Authors: Iordana Gaisidou, Giuseppe Chessa, Giannoulas Ioannis, Artur Jutman, Davide Bertozzi and Christos Sotiriou
3. Jumper: A State Capturing Element For Testability in Asynchronous Bundled-Data Circuits
   Authors: Ismael de Almeida Junior, Azzadine THAJTE, Cristiano Merio, Xavier Lesage, Adrien Godard, Ali Naimi, Sylvain Engels and Laurent Fesquet
4. Automated FPGA-Based Wafer Testing of Asynchronous FlexICs
   Authors: Marcos Luiggi Lemos Sartori, Yushu Qin, Shengyu Duan, Yujin Zheng, Rishad Shafik and Alex Yakovlev

1. ACTGen: Natural Language Assistant for Asynchronous Circuit Design
   Authors: Siva Nalabothu and Rajit Manohar
2. ALPS: An Open-Source Low-Power Bundled-Data Design Flow using Standard EDA Tools
   Authors: Cristiano Merio, Adrien Godard, Gaël Ousset, Xavier Lesage, Jéssica Gonsalves Santos, Ismael de Almeida Junior, Ali Naimi, Azzadine Thajte, Ayoub Talbi, Thierry Grollier, Marc Quast, Sylvain Engels and Laurent Fesquet

1. Easy Timers for AFSM-based Controllers in Workcraft
   Authors: Victor Khomenko and Danil Sokolov
2. Applications of asynchronous logic in power management and protection ICs
   Authors: David Cox and Filip Hormot
3. Templated and open asynchronous periphery for mixed-signal neuromorphic chips 
   Authors: Hugh Gratorex, Madison Cotterert, Michele Mastella, Arianna Rubino, Ole Richter and Elisabetta Chicca
4. Explicit Timestamp Propagation for Temporal Processing
   Authors: Xavier Lesage, Cristiano Merio, Azzadine THAJTE, Luca Sauer de Araujo, Fernando Welzel, Sylvain Engels and Laurent Fesquet

1. An Energy-Proportional, High-Speed Serial Link
   Authors: Alex Huang, Robert Soule and Rajit Manohar
2. ANP-E: A 22-nm Asynchronous Spiking Recurrent Neural Network Processor Enabling On-chip Learning for Physiological Signal Monitoring
   Authors: Yuan Hua, Chunqi Qian, Jilin Zhang and Hong Chen
3. Amplifier Circuit-based Metastability Model
   Authors: Jürgen Burin, Afsah Anjum and Andreas Steininger

Moderator: Ole Richter

1. Asymmetric Current-Starved Inverter Delay Lines for High-Performance Bundled-Data Circuits
   Authors: Jéssica Gonsalves Santos, Cristiano Merio, Adrien Godard, Ali Naimi, Robin Wilson, Sylvain Engels and Laurent Fesquet
2. Effect of Self-Timed Design Styles on the Lifetime of NEMS Circuits
   Authors: Philipp Lehninger, Andreas Steininger and Axel Jantsch
3. 74% Power Reduction in Bundled-Data Circuits Thanks to Clock Gating Integration
   Authors: Adrien Godard, Laurent Fesquet, Sylvain Engels and Robin Wilson