ASYNC 2024 Summer School

The steering committee of the IEEE ASYNC symposium is organizing a summer school on asynchronous design.  The goal of the school is to teach asynchronous chip design to students and practitioners interested in digital hardware design.  Participants will learn how to design asynchronous circuits at the behavioral level, gate level, and physical design level using design automation tools and the Skywater 130 open-source PDK.

Format:  Virtual (via Zoom), morning sessions, 9:00am to 1:00pm Eastern Time (US) (Time Zone -4:00 UTC)

Registration link: https://yale.zoom.us/webinar/register/WN__GLMFmksQTqvIbXZX3h9wg

Session 1. July 1. Behavioral design [schedule]
This session covers the abstractions used for the behavioral description of asynchronous circuits, and how one can use simulation at this level of abstraction to test the functionality of an asynchronous design.

Session 2. July 8. From behavior to gates [schedule]
This session covers systematic techniques to translate the detailed signal-level description of an asynchronous computation into gates.

Session 3. July 15. Physical design [schedule]
This session covers mapping a gate-level description of a design into a physical implementation.

Expected background: We will assume that attendees are familiar with basic logic design (level of an introductory logic design course that is taught at a University) and/or Boolean algebra/logic. We will also assume familiarity with introductory programming and scripting. We will be using a Linux environment, and so we will be assuming familiarity with simple shell scripts and standard Unix/Linux commands.