Edith Beigne, Facebook
Title – AR/VR silicon challenges and research directions – what opportunities for asynchronous design?
Abstract – Augmented reality (AR) is a set of technologies that will fundamentally change the way we interact with our environment. It represents a merging of the physical and the digital worlds into a rich, context aware and accessible user interface delivered through a socially acceptable form factor such as eyeglasses. One of the biggest challenges in realizing a comprehensive AR experience are the performance and form factor requiring new custom silicon. Innovations are mandatory to manage power consumption constraints and ensure both adequate battery life and a physically comfortable thermal envelope. This presentation reviews Augmented Reality applications at Facebook Reality Labs and Silicon challenges. We will discuss current and future Research directions and comment about some potential opportunities for asynchronous design.
Bio – Edith Beigné is the Research Director of AR/VR Silicon at Facebook Reality Labs where she leads research projects driving the future of AR devices. Her main research interests are low power digital and mixed-signal circuits and design with emerging technologies. Over the past 20 years, she has been focusing her research on low power and adaptive circuit techniques, exploiting new design techniques and advanced technology nodes for different applications ranging from high performance multi-processors to ultra-low power SoC, and, more recently, AR/VR applications. She is the chair of ISSCC 2022 and part of ISSCC TPC since 2014, she was part of VLSI symposium TPC between 2015 and 2020. Distinguished Lecturer for the SSCS in 2016/2017, Women-in-Circuits Committee chair and JSSC Associate Editor since 2018. She visited Stanford University in 2018 to research on emerging technologies and new architectures.
Kwabena Boahen, Stanford University
Title – The Future of Artificial Intelligence: A 3D Silicon Brain
Abstract – Artificial intelligence benefited from shrinking transistors and connecting them densely in two dimensions to reduce the energy cost of calculating. Now the energy cost of signaling greatly exceeds that of calculating, reducing the benefits of additional miniaturization. Signaling distance is now being shortened by stacking circuits, but stacking reduces surface area for dissipating heat, forcing a 3D processor to operate serially, rather than in parallel. A fundamental solution would exchange binary numbers, whereby each signal from a pair of units encodes one bit, for n-ary numbers, whereby each signal from an entire layer of, say, 1,024 units encodes 10 bits. These sparser and richer signals would require exchanging Boolean logic for operators inseparable in time and space. Advances in cortical physiology suggest that this inseparability could be achieved with dendrite-like detectors that weight an input based on when it occurs and where it is received. This could allow a silicon brain to scale like a biological brain in energy and heat––linearly with the number of neurons––and thus be thermally viable in 3D.
Bio – Kwabena Boahen received the B.S. and M.S.E. degrees in electrical and computer engineering from the Johns Hopkins University, Baltimore, MD, both in 1989, and the Ph.D. degree in computation and neural systems from the California Institute of Technology, Pasadena, in 1997. He was on the bioengineering faculty of the University of Pennsylvania from 1997 to 2005, where he held the first Skirkanich Term Junior Chair. He is presently Professor of Bioengineering and Electrical Engineering at Stanford University, with a courtesy appointment in Computer Science. He is also an investigator in Stanford’s Bio-X Institute and Wu Tsai Neurosciences Institute. He founded and directs Stanford’s Brains in Silicon lab, which develops silicon integrated circuits that emulate the way neurons compute and computational models that link neuronal biophysics to cognitive behavior. This interdisciplinary research bridges neurobiology and medicine with electronics and computer science, bringing together these seemingly disparate fields. His scholarship is widely recognized, with over a hundred publications, including a cover story in Scientific American featuring his lab’s work on a silicon retina and a silicon tectum that “wire together” automatically (May 2005). He has been invited to give over a hundred seminar, plenary, and keynote talks, including a 2007 TED talk, “A computer that works like the brain”, with over seven hundred thousand views. He has received several distinguished honors, including a Packard Fellowship for Science and Engineering (1999) and a National Institutes of Health Director’s Pioneer Award (2006). He was elected a fellow of the American Institute for Medical and Biological Engineering (2016) and of the Institute of Electrical and Electronic Engineers (2016) in recognition of his lab’s work on Neurogrid, an iPad-size platform that emulates the cerebral cortex in biophysical detail and at functional scale, a combination that hitherto required a supercomputer. In his lab’s most recent research effort, the Brainstorm Project, he led a multi-university, multi-investigator team to co-design hardware and software that makes neuromorphic computing easier to apply. A spin-out from his Stanford lab, Femtosense Inc (2018), is commercializing this breakthrough.
Ran Ginosar, Technion & Ramon Space
Title – Asynchronous Design for Space Applications
Abstract – Computing in Space is challenged by cosmic and solar radiation, by harsh conditions, and by the requirement for very long operational lifetime without maintenance. Some of these hardships are best addressed by asynchronous logic. I will describe the Space supercomputers made by Ramon.Space and discuss applications of various concepts that I have learned over the years from my ASYNC colleagues.
Bio – Ran Ginosar received BSc EE&CS (scl) from the Technion in 1978 and PhD from Princeton University in 1982. He served on the Technion EE & CS faculty since 1983. Ran has visited U of Utah in 1989-1990 and Intel Research in Oregon 1997-1999. He has co-founded several companies in the area of VLSI architecture. Ran is interested in computer architecture, in synchronization and in asynchronous logic research. Ran is the co-recipient of the 1998 ASYNC conference Best Paper Award.