Call for Papers  (Download

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The International Symposium on Asynchronous Circuits and Systems is the premier forum for researchers to present their latest findings in the area of asynchronous design.  Authors are invited to submit full papers on any aspect of asynchronous design, ranging from the core topics of design, synthesis and test, to asynchronous applications in system-level integration and emerging computing technologies.  Topics of interest include, but are not limited to:

1. •Asynchronous/mixed-timed circuits, architectures, memories and interfaces, including interfaces with analogue and mixed-signal domains
   

2. •Design models and methods for asynchronous buses, networks on chip (NoC), system-on-chip (SoC) and multi-chip interconnects
   

3. •Asynchronous power-adaptive computing, ultra-low power systems, electronics for energy harvesting
   

4. •Asynchrony in emerging technologies, including genetic, neural, nano and quantum computing
   

5. •Embedded system design with asynchronous architectures/implementations
   

6. •Elastic and latency-tolerant synchronous design and GALS systems
   

7. •Synchronization, arbitration, metastability modeling and analysis
   

8. •CAD tools for asynchronous design, synthesis, analysis and optimization
   

9. •Physical design of asynchronous logic and pipelines
   

10. •Formal methods for correctness, and performance/power analysis
    

11. •Test, reliability, security, and radiation tolerance
    

12. •Asynchronous variability-tolerant design and design for manufacturing
    

13. •Motivating case studies, comparisons, and applications
    

Papers will be evaluated by the program committee in a blind review process on the basis of scientific merit, innovation, relevance, and presentation.  New-idea papers are encouraged, and the program committee recognizes that such papers may contain different evaluation criteria based on the lower maturity of novel technology than papers in established areas. Accepted papers will be published in an IEEE conference proceedings.

Several selected papers with the highest review scores from the ASYNC 2010 program will be invited for submission to a Special Issue of IET Computers and Digital Techniques on the recent advances in asynchronous system design, which is planned to appear in 2011.

ASYNC 2010 will be co-located with the 4th ACM/IEEE International Symposium on Networks-on-Chip (NOCS 2010).  The organization and the programs of both symposia will be jointly coordinated, including keynote lectures, tutorials, exhibitions and social events.

Paper Format:

Papers should not exceed ten pages in IEEE double-column conference format (single-spaced, 10pt or larger font size), including figures and bibliography.  Abstracts of up to 150 words must be included, and papers should be submitted via the paper submission web site.

Important Dates:

Abstract registration:  November 30, 2009

Full paper submission:  December 7, 2009  December 14, 2009 (HARD DEADLINE)

Notification of acceptance:  February 8, 2010

Final version due:  March 1, 2010